MacBook Air 13" A2337 (820-02016) Board Repair Guide

Stage 1: Always-On Power (G3H State)

Objective: Verify battery, PPBUS_AON, and PP3V8_AON_VDDMAIN rails

Measurements:

• PPVBAT_AON_CONN: Expect 7.6V (2S) or 11.4V (3S) [VERIFY: p22] at J5150 pins 1,2,9 or C5150 pin 2.
• PPBUS_AON: Expect 8.5–12.6V [VERIFY: p23] at C5800/C5801 (68µF POLT bulk caps, page 23).
• PP3V8_AON_VDDMAIN: Expect 3.8V ±5% [VERIFY: p25-27] at U5700 output or C5840/C5841 (page 26).

Common Failures:

• No PPVBAT: Check battery connector J5150 solder joints; inspect for liquid damage; verify battery not in deep discharge.
• No PPBUS_AON: Check fuse F5200 (12A, page 23) with multimeter continuity mode. If open, probe PPBUS_AON to GND for shorts (<1Ω); suspect shorted U5700 input caps C5800/C5801 or charger U5200 output FETs Q5240/Q5265/Q5270.
• No PP3V8_AON: Measure at U5700 VIN pins (expect PPBUS_AON); check enable signal P3V8AON_PWR_EN (page 24, R5320 pull-up); use oscilloscope to verify switching at inductors L7741, L7750, L7740 (should see 500kHz-1MHz [VERIFY: p25] square wave). Check MOSFETs Q5800, Q5820, Q5840 for shorts (Drain-Source <1Ω when off = failed). Inspect feedback network R5700-series [VERIFY: p26] for open resistors.

If Stage 1 Fails:

• Action: Replace failed components (fuse, bulk caps, U5700, or associated inductors/FETs). Check for liquid corrosion under U5700 or PMU area. Verify no shorts to ground on PP3V8_AON before powering on.

Stage 2: S2 Standby Rails (S5 Wake)

Objective: Verify Master PMU outputs (PP1V8_AON, PP1V25_S2, PP1V8_S2)

Preconditions: Stage 1 passed (PP3V8_AON_VDDMAIN present).

Measurements:

• PP1V8_AON_MPMU: Expect 1.8V at U8100 LDO output (page 29, measure at C8808 [VERIFY: p29]).
• PP1V25_S2: Expect 1.25V at master PMU buck output (page 32, measure at C88A0-series caps [VERIFY: p32]).
• PP1V8_S2: Expect 1.8V at master PMU buck output (page 32, measure at C88C0-series caps [VERIFY: p32]).
• PMU_RESET_L: Expect high (~1.8V) at SoC HOLD_RESET pin (page 6) or pull-up R0791 (page 7).

Common Failures:

• No PP1V8_AON: Check PP3V8_AON at U8100 VDD_MAIN pins; verify master PMU not in reset (RESET_IN should be high, page 30); inspect for liquid damage around U8100. Measure decoupling caps C8800-series [VERIFY: p29].
• No PP1V25_S2: Verify master PMU I2C communication (I2C_SMC_PWR_SDA/SCL, page 34); check buck enable signals (SPMI control); use oscilloscope at inductor L88A0 [VERIFY: p32] to confirm switching. Check feedback resistor divider R88A0-series [VERIFY: p32].
• No PP1V8_S2: Similar to PP1V25_S2; check inductor L88C0 [VERIFY: p32] switching and feedback network R88C0-series [VERIFY: p32].
• PMU_RESET_L stuck low: Verify PPVDD_PMU_LDO_PREREG rail (page 35); check for master PMU communication errors; suspect PMU OTP corruption or internal failure.

If Stage 2 Fails:

• Action: Verify I2C communication with oscilloscope (SDA/SCL should have pull-ups and show activity during boot). If no I2C activity, check SMC or PMU. If I2C OK but no rail, replace master PMU U8100. Confirm no shorts on output rails before replacement.

Stage 3: S0 Active Rails (SoC Input Power)

Objective: Verify Slave PMU outputs and SoC input rails before core power

Preconditions: Stage 2 passed (S2 rails present).

Measurements:

• PP0V88_S1: Expect 0.88V [VERIFY: p28] at slave PMU U7700 buck4 output (measure at C7740-C7747, page 28).
• PP0V764_S1_SRAM: Expect 0.764V [VERIFY: p28] at slave PMU buck13 output (measure at C77D0-series caps [VERIFY: p28]).
• PP1V06_S2SW_DRAM: Expect 1.06V [VERIFY: p11,28] at SoC VDD2_S2 pins (measure at C1100-C1129, page 11).
• PP0V6_S1_VDDQL: Expect 0.6V at SoC VDDQL pins (measure at C1100-C1151, page 11).
• PP0V805_S1_VDD_FIXED: Expect 0.805V [VERIFY: p15] at SoC VDD_FIXED pins (page 15).

Common Failures:

• No PP0V88_S1: Verify PP3V8_AON at slave PMU U7700 VDD_MAIN pins (page 28); check buck4 enable from master PMU via SPMI (page 28); use oscilloscope at inductor L7750 [VERIFY: p28] to verify switching. Check output caps C7740-C7747 for shorts.
• No PP0V764_S1_SRAM: Check slave PMU buck13 enable; verify inductor L77D0 [VERIFY: p28] switching. Measure feedback at BUCK13_FB pin; inspect output caps C77D0-series [VERIFY: p28]. CPU SRAM will not power on without this rail.
• No PP1V06_S2SW_DRAM: Verify buck enable from master or slave PMU; check inductor switching [VERIFY: p28]; measure output caps C1100-series (4.3µF X6T, page 11). DDR will fail training without VDD2.
• No PP0V6_S1_VDDQL: Check SoC VDDQL pins (page 11); verify DDR ZQ calibration resistors R1169-R1176 (must be exactly 240Ω 1%, page 11); measure decoupling caps C1100-C1151. If rail missing, suspect SoC internal LDO failure.

If Stage 3 Fails:

• Action: If slave PMU outputs missing, verify SPMI communication between master and slave PMU (page 30); check SPMI_NUB_SPMU_CLK/DATA lines. If SPMI OK but no output, replace slave PMU U7700. If DDR rails missing, verify PMU configuration and check for shorts on SoC VDD2/VDDQL pins. If ZQ resistors wrong value, replace R1169-R1176 with exact 240Ω 1% parts.

Stage 4: CPU/GPU Core Power

Objective: Verify SoC internal buck outputs (VDD_PCPU, VDD_ECPU, VDD_GPU, VDD_SOC)

Preconditions: Stage 3 passed (all SoC input rails present).

Measurements:

• PPVDD_SOC_S1: Expect 0.7-0.95V [VERIFY: p13] at SoC VDD_SOC pins (measure at C1300-C1310, page 13).
• PPVDD_PCPU_AWAKE: Expect 0.575-1.2V dynamic [VERIFY: p13] at SoC VDD_PCPU pins (measure at C1310-C1365, page 13).
• PPVDD_ECPU_AWAKE: Expect 0.6-1.1V dynamic [VERIFY: p13] at SoC VDD_ECPU pins (measure at C1337-C1352, page 13).
• PPVDD_GPU_AWAKE: Expect 0.6-1.2V dynamic [VERIFY: p13] at SoC VDD_GPU pins (measure at C1361-C1365, page 13).
• VDD_DCS_S1: Expect [VERIFY: p14] ~0.8V at SoC memory controller (measure at C1400-C1425, page 14).

Common Failures:

• No VDD_SOC_S1: Verify PP0V805_S1_VDD_FIXED input (page 15); check decoupling caps C1300-C1310 for shorts or opens. If input rails OK, suspect SoC internal buck controller failure.
• No VDD_PCPU/ECPU/GPU: Verify all input rails (PP0V805_S1_VDD_FIXED, PP0V72_S2_VDD_LOW, etc., page 15); check sense feedback lines VDD_PCPU_SENSE, VDD_ECPU_SENSE, VDD_GPU_SENSE (page 12). Measure decoupling caps (11µF X6T 2.5V, page 13) for shorts. If rails and feedback OK, SoC has internal VR failure (not repairable—replace SoC or board).
• Low or unstable core voltage: Check decoupling capacitors for correct value and ESR; verify no excessive resistance in power plane connections. Use oscilloscope to check for ripple or oscillation (should be <50mV pk-pk [VERIFY: p13]).

If Stage 4 Fails:

• Action: If input rails present but no core voltage, inspect decoupling caps for correct value (11µF X6T 2.5V, not X5R or wrong capacitance). If caps OK, verify no shorts on SoC core power pins. If all external components OK, SoC internal buck regulators have failed—replace SoC (BGA rework) or replace board. Note: M1 SoC failures at VR level are rare; more common is liquid damage to decoupling caps or power plane corrosion.

Stage 5: I/O and Display Power

Objective: Verify I/O rails, display power, and peripheral enables

Preconditions: Stage 4 passed (SoC core power present).

Measurements:

• PP1V2_AWAKE_PLL: Expect 1.2V at filtered PLL supplies (page 15, measure at C1510-C1520 [VERIFY: p15]).
• PP1V25_AWAKE_IO: Expect 1.25V at SoC I/O pins (page 12, measure at C1233-C1244 [VERIFY: p12]).
• PP1V8_AWAKE: Expect 1.8V at display/peripherals (page 12, measure at C1200-C1213 [VERIFY: p12]).
• LPDP_INT_HPD: Check internal display HPD (hot-plug detect) signal activity (page 8).
• Backlight enables: Verify backlight power sequencer signals (pages 67-72 [VERIFY: p67-72]).

Common Failures:

• No PP1V2_AWAKE_PLL: Verify input from PMU (page 15); check filter inductors FL1510/FL1580 [VERIFY: p15] for opens; measure decoupling caps C1510-C1520. PLL power critical for SoC clocking—without it, system may not boot or have instability.
• No PP1V25_AWAKE_IO: Check master PMU output (page 12); verify load switches or LDO outputs feeding this rail. Measure at SoC VDD_IO pins; confirm no shorts.
• Display no backlight: Verify PP5V_BKLT (page 67 [VERIFY: p67]) and backlight controller U6800 [VERIFY: p67]; check enable signals from SoC (DISP_BKLT_EN, page 67 [VERIFY: p67]). Measure backlight LED string voltage (should ramp to 15-25V [VERIFY: p67]).
• No external display: Check USB-C Ace2 retimer U400/U500 [VERIFY: p49-54] power (PP0V9_ATCRTMR); verify DisplayPort AUX communication (USBC_ATC0_AUX_P/N, page 6).

If Stage 5 Fails:

• Action: If I/O rails missing, trace back to PMU outputs and check load switches U5300-series [VERIFY: p35]. If display no backlight but rail present, measure backlight controller U6800 [VERIFY: p67] input/output; check LED driver MOSFETs and inductor. For external display issues, verify USB-C port power and retimer enable signals (ATC_PWR_EN [VERIFY: p49]).

Stage 6: Peripheral and Boot Validation

Objective: Verify boot process, SPI ROM, USB-C, SSD, and final power-good

Preconditions: Stage 5 passed (all core and I/O rails present).

Measurements:

• SPI_SOCROM_CS_L: Use oscilloscope to verify toggling during boot (~10MHz clock, page 19).
• PMU_ACTIVE_READY: Should be high after all rails stabilize (page 6).
• SSD power: Verify PP0V9_NAND0_S5E0/1_VDD_PLL (page 62-63 [VERIFY: p62-63]) and PP2V5_AWAKE_NAND (page 28).
• USB-C VBUS_DETECT: Check USB_VBUS_DETECT signal (page 6) when charger connected.
• Keyboard backlight: Verify PP5V_KBD (page 75 [VERIFY: p75]) if keyboard backlight not working.

Common Failures:

• No boot (black screen, no chime): Verify SPI NOR U1970 (page 19) power (PP1V8_AWAKE); check SPI lines with oscilloscope (SPI_SOCROM_CLK should toggle at power-on). If no SPI activity, suspect SoC failure or U1970 corruption. Try reflashing U1970 with known-good iBoot firmware (requires SPI programmer and Apple firmware).
• No SSD detection: Check PP0V9_NAND0 rails (page 62-63 [VERIFY: p62-63]) and PP2V5_AWAKE_NAND (page 28); verify NAND0_RESET_L signal from SoC (page 7). Measure SSD connector for correct voltages; inspect for liquid damage.
• USB-C not charging: Verify PPDCIN_AONSW at USB-C connector (should be 5-20V when charger connected, page 49 [VERIFY: p49]); check Ace2 port controller U400/U500 [VERIFY: p49-54] communication (I2C_UPC_SDA/SCL). Measure USB_VBUS_DETECT (page 6) - should be high when VBUS present.
• Keyboard backlight not working: Check PP5V_KBD rail (page 75 [VERIFY: p75]) and backlight controller U7500 [VERIFY: p75]; verify PWM signal KBD_BKLT_PWM from SoC (page 6).

If Stage 6 Fails:

• Action: For no-boot, attempt DFU mode recovery (hold power + volume down keys [VERIFY: DFU procedure]); if DFU works, issue is software/firmware. If no DFU, suspect SoC or boot ROM U1970 failure. For peripheral issues (SSD, USB-C, keyboard), trace power rails and enable signals; check connectors for corrosion or damaged pins. Replace failed peripheral controllers or SoC if internal I/O failure.