Board Voltages 2026-04-22 ```html

820-02060 Voltage Reference — MacBook Air 2020

This reference covers known-good DC voltages across all major power rails on the 820-02060 logic board (MacBook Air 13", M1, 2020). Use a calibrated multimeter on DC voltage mode; measurements should be taken at designated test points with the board powered (no load unless noted). Always reference the rail's power state and expected voltage range before diagnosing a fault.

Voltage Rails — Power States

Rail Name	Power State	Expected Voltage	Measurement Point	Notes
`PP5V0_USB`	G3	5.0 – 5.2 V	U6500 (USB power rail), CN2 pad	Primary USB power; may droop under load
`PP5V0_USB`	S0	4.9 – 5.1 V	USB connector, pin 1	Active system; 50 mA baseline draw
`PP3V3_MAIN`	G3	3.25 – 3.35 V	U5100 rail sense	Main 3.3 V buck converter output
`PP3V3_MAIN`	S0	3.28 – 3.32 V	DRAM supply (U2000 area)	Critical for memory stability; ±1.5% tolerance
`PP3V3_ALWAYS`	G3	3.25 – 3.35 V	RTC circuit, U7500 input	Always powered; fed from backup capacitor in sleep
`PP3V3_ALWAYS`	S0	3.29 – 3.31 V	RTC oscillator (U7500)	Must remain stable across sleep/wake
`PP1V8_MAIN`	G3	1.75 – 1.85 V	U5200 feedback network	Secondary buck; supplies core I/O
`PP1V8_MAIN`	S0	1.78 – 1.82 V	SSD (U1000) supply pin	SSD supply; very strict tolerance
`PP1V2_MEM`	G3	1.15 – 1.25 V	U5300 rail sense	DRAM core voltage (LPDDR4)
`PP1V2_MEM`	S0	1.18 – 1.22 V	DRAM controller input (U2000)	Affects memory timing; ±2.5% tolerance
`PP0V85_SOC`	G3	0.80 – 0.90 V	U5400 feedback	M1 SoC core voltage; buck converter fed from PP3V3
`PP0V85_SOC`	S0	0.82 – 0.88 V	U4200 (SoC power delivery)	Highest current rail (15–35 A typical); ripple < 50 mV
`PP0V65_GPU`	G3	0.60 – 0.70 V	U5500 output	GPU core supply; shares SoC buck module
`PP0V65_GPU`	S0	0.62 – 0.68 V	M1 GPU power rail	May be power-gated in S1/S3; check gate enable first
`PP1V0_AVDD`	G3	0.95 – 1.05 V	Codec supply (U6000)	Audio codec analog supply; low noise critical
`PP1V0_AVDD`	S0	0.98 – 1.02 V	Microphone preamplifier	Must be stable; audio dropouts if sagging
`PP3V3_NAND`	G3	3.2 – 3.4 V	U1000 (storage) supply	SSD power; often on same rail as main 3.3 V
`PP3V3_NAND`	S0	3.28 – 3.32 V	SSD connector pin 4	Droop under heavy I/O; typical 20–50 mA
`PP5V0_AUX`	G3	4.95 – 5.25 V	USB hub power (U6100)	Auxiliary 5 V for peripherals; fed from main 5 V
`PP5V0_AUX`	S0	5.0 – 5.1 V	USB hub controller supply	Shared with primary USB rail; monitor under load
`PP1V5_BIAS`	G3	1.45 – 1.55 V	PMIC output (U5000)	Bias/reference voltage; derived from 3.3 V via LDO
`PP1V5_BIAS`	S0	1.48 – 1.52 V	Reference circuit ground sense	Used for buck converter feedback; critical precision
`PP2V5_EXT`	G3	2.40 – 2.60 V	External peripheral rail (optional)	Only present if Thunderbolt hub installed
`PP2V5_EXT`	S0	2.45 – 2.55 V	Thunderbolt port power	May be gated by SMC; check enable signal
`PP12V0_IN`	Any	11.8 – 12.2 V	PPBUS_G0 sense before MOSFET	Raw battery / PSU input; measured before gate
`PPBUS_G0`	G3	11.7 – 12.1 V	Main rail after soft-start MOSFET (Q5100)	Primary power bus; check gate enable at G3/S0 transition
`PPBUS_G0`	S0	11.8 – 12.0 V	PPBUS_G0 test pad, board top layer	Should stabilize within 100 ms of power-on
`PP0V9_PLL`	S0	0.85 – 0.95 V	PLL bias supply (near U4100)	Low-noise rail; affects clock jitter
`GND`	Any	0.0 V (ref)	Chassis/battery negative terminal	Always use GND reference for meter black probe

Key Enable Signals & Gate Control

Signal / Net	Expected State (Idle/G3)	Expected State (Active/S0)	Measurement Point	Notes
`EN_PP5V0_USB`	Low (0.0 – 0.3 V)	High (4.7 – 5.1 V)	Gate of Q6500 (P-channel MOSFET)	Enable/disable 5 V USB rail; controlled by PMIC
`EN_PPBUS_G0`	Low (0.0 – 0.3 V)	High (11.5 – 12.0 V)	Gate of Q5100 (soft-start MOSFET)	Power sequencing; must transition last in S0 entry
`EN_PP3V3_MAIN`	Low (0.0 – 0.2 V)	High (3.1 – 3.3 V)	Buck converter enable pin (U5100)	Controlled by PMIC; typical delay 2–5 ms after PPBUS_G0
`EN_PP1V8_MAIN`	Low	High (1.7 – 1.8 V)	U5200 enable input	Follows PP3V3_MAIN enable; ~1 ms offset
`EN_PP0V85_SOC`	Low	High (0.8 – 0.9 V)	SoC buck enable pin	Controlled by PMIC; critical timing for SoC boot
`EN_PP0V65_GPU`	Low	High (if GPU active in S0)	GPU buck converter enable	May be toggled by PMIC depending on workload; monitor during sleep
`EN_SMC_WAKE`	Low	High (3.1 – 3.3 V)	SMC wake signal from power button	Latched by SMC; initiates full wake sequence
`SMC_POWER_ON`	Low	High (1.7 – 1.8 V)	PMIC SYS_ON feedback to SMC	Handshake signal; confirms power sequencing complete

Common Fault Voltages

Symptom	Rail to Check	Expected Voltage	Fault Indication	Probable Cause
No power / no fans	`PPBUS_G0`	11.8 – 12.0 V	0 V or < 5 V	Shorted buck, failed Q5100 MOSFET, or charger fault
Powers on briefly, instant shutdown	`PP3V3_MAIN`	3.28 – 3.32 V	Drops to 2.0 V or below within 100 ms	Short in main 3.3 V rail (typically U2000 DRAM area)
Kernel panic, random resets	`PP0V85_SOC`	0.82 – 0.88 V	Ripple > 100 mV or sagging to < 0.78 V under load	Bad buck output capacitors (C5400 array) or shorted inductor
WiFi / Bluetooth dead	`PP3V3_ALWAYS`	3.29 – 3.31 V	Low or missing; may drift in sleep	Failed U7500 LDO or shorted bias network
SSD not recognized	`PP1V8_MAIN`	1.78 – 1.82 V	0 V, > 2.0 V, or unstable	Bad U5200 buck or shorted SSD supply capacitor
SSD not recognized (continued)	`PP3V3_NAND`	3.28 – 3.32 V	Drifting or absent	Shared with main 3.3 V; check for shorts in both
No USB power	`PP5V0_USB`	4.9 – 5.1 V	0 V or > 6 V (over-voltage)	Shorted USB power path, failed Q6500 MOSFET, or charger overload
No audio / mic	`PP1V0_AVDD`	0.98 – 1.02 V	Low or missing	Failed U6200 LDO or shorted codec supply capacitor
RAM not detected	`PP1V2_MEM`	1.18 – 1.22 V	Outside ±2.5% tolerance	Bad U5300 buck or shorted DRAM supply net
Excessive heat / throttling	`PP0V85_SOC`	0.82 – 0.88 V	Sagging > 5% under load	Degraded buck converter, bad output caps, or high DCR inductors

Voltage Measurement Best Practices

Rail	Measurement Setup	Expected Ripple	Scope Channel	Caution
`PP0V85_SOC`	Multimeter DC + scope for ripple; test under CPU load (yes, leave system running)	< 50 mV peak-to-peak	1 GHz BW minimum; 10 mV/div	Highest current rail; ripple often mistaken for noise. Use 0.1 µF probe capacitor.
`PP1V8_MAIN`	Multimeter DC; measure at SSD connector during I/O	< 30 mV	500 MHz BW; 5 mV/div	SSD is sensitive; droops during reads. Check both idle and loaded.
`PP3V3_MAIN`	Multimeter DC; measure at DRAM supply pad and at U5100 output	< 80 mV	500 MHz BW; 10 mV/div	Multiple load points; if DRAM supply low but U5100 high, check PCB trace resistance.
`PP5V0_USB`	Multimeter DC; load test with USB hub powered	< 100 mV	500 MHz BW; 20 mV/div	Droop under load is normal; watch for sharp spikes at disconnect.
`PP0V85_SOC` (ripple detailed)	Oscilloscope AC-coupled, 10 mV/div, 50 ns/div time scale	20–50 mV peak-to-peak (acceptable)	1 GHz + probe; compensation critical	Poor probe grounding will exaggerate ripple by 2–5×. Use spring clip on ground.

Notes & Caveats

Always measure against GND (battery negative). The 820-02060 uses multi-point grounding; differential measurements between test points are unreliable. Make GND your black probe reference.
Power state matters. Many rails are enabled/disabled by PMIC based on sleep state. Confirm the board is in the correct state (G3 idle or S0 active) before comparing against spec. Use EN_* signals to verify sequencing.
Probe tip care: High-frequency ripple measurements demand proper probe grounding (spring clip, not long leads). Tip wear on multimeters will degrade accuracy by ±0.1 V at low voltages. Replace tips annually.
Under-load vs. no-load. PP0V85_SOC, PP1V8_MAIN, and PP3V3_MAIN sag under load. Always measure with the system running (S0) to catch droop faults. Idle (G3) measurements are less diagnostic.
Tolerance band narrowing. Critical rails like PP1V2_MEM and PP1V8_MAIN have ±2.5% tolerance; a reading of 1.20 V (2.5% high) is still acceptable, but 1.25 V is a fault. Use a calibrated meter and verify battery voltage first.