Tools & Settings 2026-04-10

Oscilloscope Settings for Board Repair — Quick Reference

Fast lookup for scope settings (time/div, voltage/div, probe attenuation, coupling) when troubleshooting Apple logic boards. Use these as starting points; adjust based on signal frequency and amplitude. All settings assume a standard 4-channel digital oscilloscope (Rigol, Keysight, Siglent, or equivalent).

Power Rails & DC Monitoring

Rail / Signal	Voltage Range	Voltage/Div	Probe Atten.	Coupling	Time/Div	Notes
`PP3V3` (main 3.3 V rail)	3.0–3.6 V	0.5 V/div or 1 V/div	1×	DC	100 ms/div (static)	Set DC coupling to see droop during transients. Look for ripple < 50 mV.
`PP5V0` (USB / peripheral 5 V)	4.7–5.3 V	1 V/div or 2 V/div	1×	DC	100 ms/div (static)	High ripple indicates regulator or capacitor failure. Monitor during USB attach.
`PP1V8_S0` (core 1.8 V)	1.6–2.0 V	0.2 V/div or 0.5 V/div	1×	DC	50 ms/div (static)	Most sensitive rail. Small droop indicates load transient or short. Watch for noise.
`PP1V2_S0` (PLL 1.2 V)	1.0–1.4 V	0.2 V/div	1×	DC	50 ms/div (static)	Used on older Intel boards. Dropout < 50 mV acceptable.
`PP0V85_S0` (CPU/GPU core)	0.75–0.95 V	0.1 V/div or 0.2 V/div	1×	DC	50 ms/div (static)	Lowest voltage rail — highest sensitivity required. Droop > 100 mV is critical.
`PP1V05_S0` (RAM rail)	0.95–1.15 V	0.2 V/div	1×	DC	50 ms/div (static)	Memory supply. Ripple typically < 30 mV. Check during boot sequence.
`PP3V3_S0` (S0 always-on 3.3 V)	3.0–3.6 V	0.5 V/div	1×	DC	100 ms/div (static)	Powers SMC, PMIC. Present even in sleep. Dropout indicates MOSFET short.
`PP2V5` (analog/audio)	2.3–2.7 V	0.5 V/div	1×	DC	100 ms/div (static)	Audio codec supply. High ripple causes audio noise. Separate ground return.
`PP1V5` (DDR memory I/O)	1.35–1.65 V	0.2 V/div	1×	DC	50 ms/div (static)	LPDDR rail. Absence causes memory errors, no POST. Check at PMIC output.
`PPBUS_G3H` (unregulated battery bus)	0 (off)–12.6 V (max)	2 V/div or 5 V/div	1× or 10×	DC	100 ms/div (static)	Primary input. Use 10× probe if measuring > 20 V. Monitor during power-on.

Clock & Crystal Signals

Signal / Component	Frequency	Amplitude	Voltage/Div	Time/Div	Probe Atten.	Coupling	Notes
`OSC_24MHZ` main oscillator	24 MHz	3.3 V peak	1 V/div	50 ns/div	1×	AC	Sine wave. Look for clean zero crossings. Duty cycle ~50%. Jitter < 100 ps.
`OSC_32KHZ` RTC oscillator	32.768 kHz	3.3 V peak (CMOS logic)	1 V/div	50 µs/div	1×	AC	Square wave. Check with external 32 kHz counter. Absent = SMC/RTC chip dead.
`CLK_SHUTDOWN` SMC clock	1–5 MHz	0 V–3.3 V CMOS	1 V/div	1 µs/div	1×	AC	Stops when SMC enters sleep. Confirm via PWM or LPC activity during shutdown.
`REFCLK` PCH/FCH reference	100 MHz or 133 MHz	0 V–3.3 V LVPECL or LVCMOS	1 V/div	20 ns/div	1×	AC	Very fast. Use 200 MHz+ scope bandwidth minimum. Jitter critical for memory stability.
`MEMCLK` DDR memory clock	400–800 MHz (DDR3/DDR4)	LVDS differential	0.2 V/div (differential)	2 ns/div	1×	AC	Use differential probe. Scope BW ≥ 2× signal freq. Look for eye diagram closure.
`CPU_CLK` processor clock	2–5 GHz	LVDS	0.1 V/div (differential)	500 ps/div	1×	AC	Requires high-speed differential probe and ≥ 6 GHz scope. Measure at CPU pins.

Logic & Signal Integrity

Signal Type	Voltage Logic (typ.)	Voltage/Div	Time/Div	Probe Atten.	Coupling	Trigger Type	Notes
CMOS 3.3 V (GPIO, chipset)	0 V (low) / 3.3 V (high)	1 V/div	1 µs/div (typical frame)	1×	DC	Rising or falling edge	Standard logic. Check for overshoot > 0.5 V or ringing. Measure at pad, not trace.
CMOS 1.8 V (core signal)	0 V (low) / 1.8 V (high)	0.5 V/div	1 µs/div	1×	DC	Rising or falling edge	Lower voltage = higher noise sensitivity. Look for clean 10–90% transitions.
LVCMOS (LPC, I2C)	0 V (low) / 3.3 V (high)	1 V/div	10 µs/div (protocol frames)	1×	DC	Bus idle (high) or activity trigger	Open-drain / open-collector. Measure pull-up voltage. Check rise time.
I2C/SMBus clock (`CLK_SMC`)	0 V / 3.3 V (open-drain)	1 V/div	100 µs/div or 200 µs/div	1×	DC	Falling edge or pulse width trigger	Typical freq: 100–400 kHz. Measure rise time ≥ 1 µs (due to pullup RC). Check for stuck low.
I2C/SMBus data (`DATA_SMC`)	0 V / 3.3 V (open-drain)	1 V/div	100 µs/div or 200 µs/div	1×	DC	Data transition or protocol trigger	Setup/hold time critical. Use protocol trigger if available. Watch for metastable states.
SPI clock (`CLK_SPI`)	0 V / 3.3 V CMOS	1 V/div	100 ns/div to 1 µs/div	1×	DC	Rising or falling edge	Typical: 10–50 MHz. Check duty cycle ~50%. Look for jitter near clock edges.
SPI data (`MOSI`, `MISO`)	0 V / 3.3 V CMOS	1 V/div	100 ns/div to 1 µs/div	1×	DC	Sync to `CLK_SPI`	Capture bursts (frames) in single-shot mode. Check setup/hold vs. clock.
UART TX / RX	0 V / 3.3 V CMOS	1 V/div	10 µs/div or 100 µs/div (baudrate dependent)	1×	DC	Serial protocol trigger (if available)	115200 baud typical. 1 bit ≈ 8.7 µs. Use logic analyzer for protocol decode.
LPC (Low Pin Count) clock	0 V / 3.3 V CMOS	1 V/div	1 µs/div	1×	DC	Rising or falling edge	Typical: 33 MHz. Measure frequency on SMC side. Absent or very slow = PCH/SMC issue.
LPC data (LFRAME, LAD[3:0])	0 V / 3.3 V CMOS	1 V/div	1 µs/div	1×	DC	Protocol or sync to LPC clock	4-bit bus. Measure all lines simultaneously if possible. Check for timing skew.

Power Management Signals

Signal / Line	Active State	Voltage	Voltage/Div	Time/Div	Coupling	Notes
`POWER_BTN` (power button)	Low (active)	0 V (pressed) / 3.3 V (released)	1 V/div	100 ms/div	DC	Debouncing required. Look for clean logic, minimal bounce (< 50 ms).
`SMC_ENABLE` or `SYS_PWREN`	High (enable) or Low (enable)	0 V / 3.3 V CMOS	1 V/div	10 ms/div (power sequence)	DC	SMC output controlling primary PMIC. Timing critical: measure ramp, not just logic state.
`PCH_PWRGD` (power good)	High (good)	0 V (bad) / 3.3 V (good)	1 V/div	10 ms/div	DC	Chipset signal to CPU. Delayed after rail stable. Stuck low = regulator issue.
`CPU_PWRGD` or `VCOREOK`	High (good)	0 V / 3.3 V CMOS	1 V/div	10 ms/div	DC	CPU core rail quality indicator. Absence blocks boot. Check against `PP0V85` ramp.
`RESET_L` or `RST_SYSTEM`	Low (active reset)	0 V (reset) / 3.3 V (normal)	1 V/div	10 ms/div (power-on) to 1 µs/div (signal detail)	DC	Must be high for normal operation. Measure rise time (should be clean). Pulse width > 1 µs on release.
`SLEEP_L` (S3 sleep signal)	Low (sleep)	0 V (sleep) / 3.3 V (awake)	1 V/div	100 ms/div	DC	From CPU to chipset. Low = S3 mode (lower power). Check for stuck low (wake issue).
`PCI_CLKREQ_L` (PCIe link request)	Low (active)	0 V (active) / 3.3 V (idle)	1 V/div	1 ms/div	DC	Controls PCIe clock. Multi-device line. Look for toggling during device activity.
`S0_VCORE_PG` (S0 VCORE power good)	High (good)	0 V / 3.3 V	1 V/div	5 ms/div	DC	Delayed feedback from PMIC. Missing = regulator failure. Check settling time after PP0V85 stable.

Regulator & Switched-Mode Power Supply (SMPS)

Measurement / Point	Signal / Rail	Frequency	Voltage/Div	Time/Div	Probe Atten.	Coupling	Notes
PMIC PWM gate drive	`SW_NODE` (high-side MOSFET drain)	300 kHz–2 MHz (typ.)	2 V/div or 5 V/div	500 ns/div to 2 µs/div	1×	DC	High-speed square wave. Check ringing, overshoot, duty cycle. Measure rise/fall time.
PMIC feedback (divider)	`FB_NODE` (feedback pin to PMIC)	< 10 kHz (feedback loop BW)	0.2 V/div or 0.5 V/div	100 µs/div	1×	DC	Slow DC voltage with AC ripple. Nominal ~0.6 V. Large ripple = capacitor ESR high.
PMIC output (filtered)	`VOUT` of regulator (e.g., `PP3V3_S0`)	Static + switching ripple (10–100 kHz)	0.5 V/div or 1 V/div	100 µs/div (ripple) or 10 ms/div (transient)	1×	DC	Observe DC level + AC ripple. Ripple typ. 30–100 mV peak-to-peak. Measure near load.
Inductor current (sense)	`ISEN` (current sense resistor)	Same as PWM freq. (300 kHz–2 MHz)	0.5 V/div or 1 V/div	500 ns/div to 2 µs/div	1×	AC (preferred) or DC	Triangular waveform. Measure peak voltage across sense resistor (typ. 10–100 mV). Check for distortion.
Bootstrap cap voltage	`BST` (bootstrap node, high-side gate driver)	Slow ripple overlaid on PWM ripple	1 V/div or 2 V/div	1 µs/div (switching detail) or 10 ms/div (overall trend)	1×	DC	Typically 5–8 V above SW node. Large droop = cap ESR or leakage. Low = gate drive weak.

Common Scope Settings by Troubleshooting Scenario

Scenario	Primary Signal	Voltage/Div	Time/Div	Bandwidth Req.	Trigger Mode	Quick Check
Board won't power on	`PPBUS_G3H`, `PP3V3_S0`, `POWER_BTN`	1–2 V/div	100 ms/div	≥ 20 MHz	Edge trigger on `POWER_BTN` falling	Confirm `PPBUS` present, `PP3V3_S0` rises when button pressed. Look for hold time.
SMC not responding / no dock recognition	`LPC_CLK`, `SMC_SDA`, `SMC_SCL`	1 V/div	1–10 µs/div	≥ 50 MHz	Rising or falling edge on clock	Check `LPC_CLK` frequency (~33 MHz). If absent or < 1 MHz, SMC is dead.
CPU boots then hangs or crashes	`PP0V85`, `PP1V05`, `CPU_CLK`	0.1–0.2 V/div (core rail)	1–5 µs/div	≥ 100 MHz (minimum)	Trigger on `CPU_CLK` or edge	Monitor core rail during hang. Watch for droop > 200 mV, oscillation, or collapse.
Memory errors / kernel panic	`MEMCLK`, `PP1V5`, `REFCLK`	0.2 V/div (differential on MEMCLK)	2–5 ns/div	≥ 1 GHz (for eye diagram)	Rising edge on `REFCLK`	Check memory rail voltage, clock jitter, eye closure. Use diff. probe on MEMCLK.
USB / external device not recognized	`PP5V0`, `USB_DP`, `USB_DM`	1–2 V/div (power), 1 V/div (signal)	10 µs/div (protocol) or 100 ms/div (power)	≥ 50 MHz	Rising edge on `USB_DP` or `USB_DM`	Confirm `PP5V0` > 4.7 V. Check USB line levels (~3.3 V CMOS or LVTTL). Look for noise.
Audio distortion / no sound	`PP2V5`, audio clocks, analog I2S lines	0.5 V/div (power), 1 V/div (signal)	10 µs/div	≥ 50 MHz	Free-run or edge trigger on MCLK	Check `PP2V5` ripple (should be low). Measure I2S clock (MCLK, LRCK, SCLK) frequencies.
Thermal shutdown / restart loops	`PP3V3_S0`, `PP0V85`, `RESET_L`	0.5 V/div (rails), 1 V/div (reset)	10 ms/div to 100 ms/div	≥ 20 MHz	Trigger on `RESET_L` falling (restart event)	Watch power rails for dropout or slow ramp. Check for excessive ripple or oscillation before reset.
GPU / discrete video not detected	`PCIEX16_CLK`, `PCIe_CLKREQ_L`, `GPU_PWR`	1 V/div	1–10 µs/div	≥ 100 MHz	Rising edge on clock or request signal	Confirm PCIe reference clock present. Check CLKREQ toggling. Monitor GPU power rails.
SSD not recognized / slow boot	`SPI_CLK`, `SPI_CS_L`, `SPI_MOSI`, `SPI_MISO`	1 V/div	100 ns/div to 1 µs/div	≥ 50 MHz	Sync to `SPI_CS_L` falling (frame start)	Capture SPI bursts in single-shot. Check clock freq. (typ. 10–50 MHz). Look for timing skew.

Probe Specifications & Selection

Probe Type	Attenuation	Input Z (typical)	Bandwidth (typical)	Best Use Case	Setting on Scope	Notes
1× passive	1:1	1 MΩ \|\| 20 pF	≤ 100 MHz	Low-speed logic, slow power rails	`1×` (probe menu)	Standard probe. Loads circuit slightly. Ground clip essential. Good for DC measurements.
10× passive	10:1	10 MΩ \|\| 12 pF	≤ 500 MHz	Higher voltage signals (> 20 V), PMIC output	`10×` (probe menu)	Less capacitive loading. Requires longer rise time. Scale scope reading ÷ 10.
Active differential	1:1	~1.5 MΩ differential	≤ 2 GHz	DDR clock, CPU clock, high-speed diff. pairs	`Differential` (ch. B–A math)	Removes common-mode noise. Battery-powered. Requires power connector. Expensive.
Current probe (clamp)	Variable (typ. 1 A/div)	N/A (measures via mag. coupling)	100 kHz–10 MHz	Regulator current, transient current draw	Scope-dependent; check manual	Non-invasive. Clip around wire or PCB trace. Check frequency range vs. SMPS freq.
FET probe (voltage)	1:1	High (> 10 MΩ)	≤ 1 GHz (varies)	Low-current nodes, high-impedance signals	`1×`	Minimal capacitive loading. Good for analog circuits. More expensive than passive.

Oscilloscope Dial & Menu Reference

Setting / Menu	Recommended Default	Adjust When	Common Values
Acquisition Mode	Normal	Noise is high, or capturing rare events	Normal, Average (4–16 frames), Peak Detect, High Resolution
Sample Rate	Auto (oscilloscope determines)	Aliasing suspected, or high detail required	Manual setting: ≥ 5× signal max frequency. E.g., for 100 MHz signal, use 500 MS/s min.
Record Length	Maximum available	Longer time capture needed (> 1 ms)	Rigol: 24k, Keysight: 1M, Siglent: 14M (check spec sheet)
Trigger Level	50% of signal amplitude (middle of transition)	Signal jitter, noise, or to capture specific event	For 3.3 V logic: ~1.65 V. For 1.8 V logic: ~0.9 V.
Trigger Coupling	DC (for power rails), AC (for clocks)	DC offset blocking required, or high-frequency noise	DC, AC, LF Reject, HF Reject
Trigger Source	Ch 1 (or primary signal)	Multiple signals, or sync to external event	Single channel, OR logic of multiple channels, External (EXT)
Trigger Slope	Rising (↗)	Falling edge event required	Rising, Falling, or Pulse (width-based)
Vertical Coupling	DC (default)	Large DC offset obscures AC ripple	DC, AC, Ground (zero reference)
Impedance (input)	1 MΩ (for most probes)	50 Ω termination for RF / high-speed	1 MΩ (standard), 50 Ω (coax termination)
Math / Ch A – Ch B	Disabled	Differential measurement, or difference check	Add, Subtract, Multiply, Divide, FFT

Notes & Caveats

Probe Placement: Always attach ground clip or use short ground wire (< 1 inch). Long ground leads = inductive coupling, ringing, and false readings. Measure as close to the component under test as possible; avoid measuring mid-trace if high impedance path exists.
Compensation & De-skew: Before measuring, compensate passive probes using the scope's square-wave calibration output. Verify each channel is de-skewed (< 50 ps) if measuring multiple signals simultaneously.
Bandwidth & Aliasing: If scope bandwidth is < 5× the signal frequency, expect aliasing and false waveforms. For 500 MHz clocks, require ≥ 2.5 GHz scope minimum; for 100 MHz signals, ≥ 500 MHz is acceptable.
DC Coupling on Fast Signals: When measuring fast edges (clocks, SPI, UART), use DC coupling to capture the full transition. AC coupling removes the baseline and may hide bias or DC offset issues.
Averaging & Noise: For noisy rails (ripple, EMI), enable Average mode (4–16 captures) to see the true signal beneath noise. Use Peak Detect mode to capture glitches or rare spikes.
Trigger Sensitivity: If the trigger won't lock, reduce trigger coupling (try HF Reject), or manually adjust level. Avoid setting trigger at the very edge of the waveform; use 50% point for stability.